Conventional SOI FETs offer advantages over bulk devices, but they also offer a distinct disadvantage. The advantages include latchup immunity, radiation hardness, reduced junction capacitance, and reduced junction leakage currents. In addition fully depleted SOI devices offer additional advantages. They provide reduced short channel effect, near ideal sub-threshold slope, increased transconductance, and reduced threshold voltage (Vt) sensitivity to changes in body doping, channel length, temperature, and substrate voltage. Additional advantages are that the kink effect and Vt shifts caused by body charging are significantly reduced in fully depleted devices compared to partially depleted devices. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin that the entire thickness of the body region is depleted of majority carriers when in the off state and both diffusions are at ground.
But conventional SOI FETs have a "floating body" in which the body or channel region of the FET is located on insulator and not electrically connected to a fixed potential. Floating body SOI devices can experience high leakage current and parasitic bipolar action. This disadvantage can be eliminated by providing a contact to the substrate or to the starface to tie the body to a fixed potential.
Body-substrate contacts for SOI devices have been formed located under the gate, as illustrated in U.S. Pat. Nos. 4,396,933 to Magdo et al. ("the '933 patent"), and 4,814,287 to Takemoto et al. ("the '287 patent"). However, with SOI devices having the body-substrate contact in the channel region, the gate remains capacitively coupled to both bulk charge and SOI charge, detracting from the advantages of an SOI structure.
In addition to the capacitive coupling problem, applicants found that substrate bias sensitivity in a DRAM cell is about as high for SOI devices with a body-substrate contact in the channel region as for bulk devices. Source to substrate voltage, the back bias, increases as the node is charged (the node is the transistor electrode tied to the cell capacitor. When writing a high level to the capacitor, the node is the source of the transistor). Depending on the substrate sensitivity, as this back bias increases, Vt increases. With fixed gate potential, the device starts turning itself off as the node potential increases due to increasing Vt and decreasing Vgs. This means that a higher gate potential is needed to keep the device on. To provide a higher gate potential, the chip must be designed with a higher wordline voltage (Vgs). However, a higher Vgs introduces reliability concerns such as hot electron effects and gate-dielectric breakdown. All else being equal, a chip with a higher Vgs dissipates more power, a major problem for high speed logic and memory chips. Thus, by not obtaining the reduced substrate sensitivity available to SOI devices, key performance advantages of SOI are sacrificed in these previous attempts to achieve a body-substrate contact.
Other schemes for body contact require that the channel region have a heavily doped layer over the insulation, and these schemes, like the body contacts illustrated by the '933 and '287 patents, permit bulk charges always to be available, preventing the device from reaching full depletion. Still other schemes have a body contact to the surface that adds significantly to chip area, defeating some of the advantage of SOI.
Thus, the prior art has provided SOI structures having a floating body. The prior an has also attempted to solve the floating body problem by providing body contacts. But the body contacts of the prior art either are located so that they avoid using additional chip area but prevent full depletion, or are located so that they consume a significant amount of additional chip area. Therefore, improvement is needed to retain the advantages of SOI without the disadvantages either of the floating body or of other schemes for a body contact.